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Is procedural continuous assignment statement synthesizable or not?

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ankit12345

ankit12345

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I heard that assign using wire is synthesisable..........It?????

Any one tried????
 

Re: Assign in verilog

ankit12345 said:
I heard that assign using wire is synthesisable..........It?????

Any one tried????
Click to expand...

Of-course it is, a simple MUX code:

Code: 
assign out_val = sel ? in_1 : in_2;

In general assign is a good candidate for simple combinatorial logic description.

HTH
Ajeetha, CVC
www.noveldv.com
 

Assign in verilog

Sorry......the question is wrong.........
Its not what i mean........

I will post the exact question soon
 

Assign in verilog

It is synthesizable, and with "assign" statemetnt, the code is easy to modify and maintain. But some times, it may cause some problems in backend tools.
 

Assign in verilog

My exact ? is weather PROCEDURAL CONTINOUS ASSIGNMENT statement is synthesizable r not???
 

Assign in verilog

yes...i have tried using quatusII for altera...
but you need to know code that can be synthesize...
 

Re: Assign in verilog

ankit12345 said:
My exact ? is weather PROCEDURAL CONTINOUS ASSIGNMENT statement is synthesizable r not???
Click to expand...

it depends, "assign" is synthesizable.
procedural-continuous assignment containing event or delay is not synthesizable.
 

Re: Assign in verilog

ankit12345 said:
My exact ? is weather PROCEDURAL CONTINOUS ASSIGNMENT statement is synthesizable r not???
Click to expand...

As per IEEE 1364.1, this is NOT synthesizable, may I know where you see a need for it in RTL modeling? I believe it can be worked around.

Ajeetha, CVC
www.noveldv.com
 

Re: Assign in verilog

Hello!
With assign help has possible realize the combinational logic !
 

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