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    Opamp design for amplifying input common mode voltage

    Hi all,
    Please refer the following diagram of two stage opamp..Vdd = 1.8V, Vbias = 1.234V, Cload = 35pF



    When I give 900mV as input to both input terminals the output is 900mV and all the transistors are in saturation.
    My problem is:
    1When I connect it in non inv. config. with resistive feedback(Rf = 1K, R1 = 1K) I get 100mV out if input is 1V..Not working as amplifier..
    2. How to find the offset voltage of opamp in cadence
    Thanks in advance
    BR
    Vabzter

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    Re: Opamp design help

    1> You cannot use a CMOS OPA as a Bipolar one!
    as I know, different with Bipolar OPA, CMOS OPA have low current drive capability, it can not drive a 1K resistor! usually we use capacitor (such as mos gate) as a loading. maybe you can find detail in Paul Gray's book.



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  3. #3
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    Re: Opamp design help

    Quote Originally Posted by butterfish
    1> You cannot use a CMOS OPA as a Bipolar one!
    as I know, different with Bipolar OPA, CMOS OPA have low current drive capability, it can not drive a 1K resistor! usually we use capacitor (such as mos gate) as a loading. maybe you can find detail in Paul Gray's book.
    Hi butterfish
    Thanks for your comments..That means the feedback network must be capacitve?
    BR
    Vabzter



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    Re: Opamp design help

    Quote Originally Posted by Vabzter
    Quote Originally Posted by butterfish
    1> You cannot use a CMOS OPA as a Bipolar one!
    as I know, different with Bipolar OPA, CMOS OPA have low current drive capability, it can not drive a 1K resistor! usually we use capacitor (such as mos gate) as a loading. maybe you can find detail in Paul Gray's book.
    Hi butterfish
    Thanks for your comments..That means the feedback network must be capacitve?
    BR
    Vabzter
    it should have a high input impedence, means you loading should match with the drive capability.



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    Opamp design help

    Vabzter
    Your output stage has a large output resisitor , and thus you get a large DC gain. The feedback resistor is paralleled with your opamp's output resisitor, thus the output resisitor is significantly reduced and the dc gain lost much.



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    Re: Opamp design help

    Hi,
    I want to design an opamp which will amplify from 1.2V to 1.7V. Is a simple two stage opamp as above sufficient for this application?
    BR
    Vabzter



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    Opamp design help

    Vabzter
    1.2v to 1.7v,power supply voltage or input common mode voltage?



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    Re: Opamp design help

    Quote Originally Posted by paladinzlp
    Vabzter
    1.2v to 1.7v,power supply voltage or input common mode voltage?
    Hi,
    Its input common mode voltage..the supply is at 1.8V
    BR
    Vabzter



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    Re: Opamp design help

    Quote Originally Posted by Vabzter
    Hi all,
    Please refer the following diagram of two stage opamp..Vdd = 1.8V, Vbias = 1.234V, Cload = 35pF

    [img]h**p://images.elektroda.net/5_1170060353_thumb.jpg[/img]

    When I give 900mV as input to both input terminals the output is 900mV and all the transistors are in saturation.
    My problem is:
    1When I connect it in non inv. config. with resistive feedback(Rf = 1K, R1 = 1K) I get 100mV out if input is 1V..Not working as amplifier..
    2. How to find the offset voltage of opamp in cadence
    Thanks in advance
    BR
    Vabzter

    Connect your opamp output to a gate of a Nmos. Use the source of Nmos to drive the resistive load. To drive resistive load, u need a low out impedance. Only source of Nmos can provide u 1/gm impedance which is very low. And also make sure the Nmos able to source that much of current to the resistive load.



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    Re: Opamp design help

    refer to allen holberg book chapter 6 and 7.



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