shakeebh
Member level 2
gtech verilog model
Hi all
I have a verilog design described in dataflow model and want to convert it into equivalent gate level description. Is there any tool that can automate the task? And will ModelSim be able to do it?
Thanks
Hi all
I have a verilog design described in dataflow model and want to convert it into equivalent gate level description. Is there any tool that can automate the task? And will ModelSim be able to do it?
Thanks