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Newbie questions about Layout

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electronics_sky

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I am a newbie in Layout. Hope anyone can help me to answer the question below:

1. Why should we separate 2 metal lines far apart? Except to avoid shortening and crosstalk.
2. If a DRC for spacing of 2 metal is "x", why sometime we need to make it for greater than x?
3. What are the important of maintaining the symetry of layout?
4. What is matching in layout? is it about Symmetry and common centroid between devices ?
5. What are the things that we need to consider when drawing a analog/digital layout?
6. what is "finger" in layout?
7. How to minimise the area of layout? except share the diffusion of transistor?
8. What is the most concern issue of a layout engineer?
9. What are the effect of crosstalk? induce noise?
10. How is one evaluate a layout? What aspect we should look into? parasitic resistance/capacitance/inductance? what more?

Please kindly add in any information that a newbie should know.

thanks a lot.

cheers!
 

Re: Good Layout

Hi Guy i have figure out the answer myself, please correct me if i am wrong.

1. Why should we separate 2 metal lines far apart? Except to avoid shortening and crosstalk.

Apart from that, due to the inefficient/nonideal in fabrication process, the edge of the metal is not a straight line. However they are like a "saw". So this may cause both metal to short together.

Crosstalk is due to the parasitic/fringing capacitance between the 2 metals. This capacitance will degrade the propagation delay of the signal.

2. If a DRC for spacing of 2 metal is "x", why sometime we need to make it for greater than x?

In analog design we normally does not follow the minimum DRC spacing. Because analog layout is much more senstive than digital layout. Just to avoid the effect of parasitic capacitance . .....Pleas comment about this!

3. What are the important of maintaining the symetry of layout?

- introduced input refer offset.....please comment about this.
-symetry may also suppress the effect of common mode noise and even order non linearity.

4. What is matching in layout? is it about Symmetry and common centroid between devices ?

basically it is about the symetry of this layout but accordign to the direction of current flow instead of the orientation of the layout.

Common centroid is usually use to match layout. One reason why common centroid is used because symetry becomes more difficult to establish for large transistor. The idea of common centroid is to decompose each transistor into two halves that are placed diagonally opposed to each other and connected in parallel.


5. What are the things that we need to consider when drawing a analog/digital layout?

I would say the most important thing to prevent is the crosstalk and fringing capacitance cause by the layout.

6. what is "finger" in layout?

a technique used to "folded" the transistor in order to reduce both S/D junction are and gate resistance.As a rule of thumb, the width of each finger is chosen such that the resistance of the finger is than 1/gm.

While the gate resistance can be reduced by using more finger but capacitance associated with the perimeter of the S/D are increases.


7. How to minimise the area of layout? except share the diffusion of transistor?

That is the only way i can think of now.

8. What is the most concern issue of a layout engineer?

Please refer 1-5

9. What are the effect of crosstalk? induce noise?

induce noise and cause delay.

10. How is one evaluate a layout? What aspect we should look into? parasitic resistance/capacitance/inductance? what more?

Does the layout will result signaficant RLC that will violate the specification. For example additional parasitic cap will cause delay.

Thank you. Please correct me if i am wrong. Any useful comment/idea would be much appreciated.

Many thanks
 

Re: Good Layout

hi ,
other than this take care of vias size, ground , stacking of layer,clock distribution,terminators.....
Regards
Shailendra Shukla
 

Good Layout

Latch up will be considered.
 

Re: Good Layout

electronics_sky said:
Hi Guy i have figure out the answer myself, please correct me if i am wrong.

1. Why should we separate 2 metal lines far apart? Except to avoid shortening and crosstalk.

Apart from that, due to the inefficient/nonideal in fabrication process, the edge of the metal is not a straight line. However they are like a "saw". So this may cause both metal to short together.

Crosstalk is due to the parasitic/fringing capacitance between the 2 metals. This capacitance will degrade the propagation delay of the signal.

2. If a DRC for spacing of 2 metal is "x", why sometime we need to make it for greater than x?

In analog design we normally does not follow the minimum DRC spacing. Because analog layout is much more senstive than digital layout. Just to avoid the effect of parasitic capacitance . .....Pleas comment about this!

3. What are the important of maintaining the symetry of layout?

- introduced input refer offset.....please comment about this.
-symetry may also suppress the effect of common mode noise and even order non linearity.

4. What is matching in layout? is it about Symmetry and common centroid between devices ?

basically it is about the symetry of this layout but accordign to the direction of current flow instead of the orientation of the layout.

Common centroid is usually use to match layout. One reason why common centroid is used because symetry becomes more difficult to establish for large transistor. The idea of common centroid is to decompose each transistor into two halves that are placed diagonally opposed to each other and connected in parallel.


5. What are the things that we need to consider when drawing a analog/digital layout?

I would say the most important thing to prevent is the crosstalk and fringing capacitance cause by the layout.

6. what is "finger" in layout?

a technique used to "folded" the transistor in order to reduce both S/D junction are and gate resistance.As a rule of thumb, the width of each finger is chosen such that the resistance of the finger is than 1/gm.

While the gate resistance can be reduced by using more finger but capacitance associated with the perimeter of the S/D are increases.


7. How to minimise the area of layout? except share the diffusion of transistor?

That is the only way i can think of now.

8. What is the most concern issue of a layout engineer?

Please refer 1-5

9. What are the effect of crosstalk? induce noise?

induce noise and cause delay.

10. How is one evaluate a layout? What aspect we should look into? parasitic resistance/capacitance/inductance? what more?

Does the layout will result signaficant RLC that will violate the specification. For example additional parasitic cap will cause delay.

Thank you. Please correct me if i am wrong. Any useful comment/idea would be much appreciated.

Many thanks
Click to expand...

2) also to reduce the risks of faults. Metal widths are also larger to reduce electromigration.

3) keeping a good symmetry is important to make "the most similar" things that are supposed to be equal. But what really matters is the "axial" symmetry: that is use common centroid whenever possible. Also a symmetric layout introduces the same parasitics in paths supposed to be equal. This reduces offsets, distortion, crosstalks, and increases rejections.

6) electronics_sky: could you please develop your statement: R~1/gm. Which R?

7) another way to reduce layout size is to abutt diffusions if supported by the process.

9) crosstalk can also increase distortion (IPx terms) and it basically reduces SNR

I would add keep an eye over the VDD and GND drop. Also in some noise sensitive circuits (ADCs, low noise amps, VCOs, etc) you can add some decoupling capacitors just aside the power terminals of your block (discuss it with the designer). Another impotant point is the way you ditribute the power signals. Keep a star-like structure whenever possible.

Whoa, we can talk for ours about layout:) I'll let others say what they think. This is a very interesting point no much considered by designers that do not make layout. I think that the best is to have the same person making the design and the layout (at least during a while) to really understand the layout issues.
 

Good Layout

also the bulk connection of the X'tors need to be varified from Designer as many times bulk is physically connected to VSS but in edit form of the instance it shows something else.
 

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