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Oscillator 100MHz and two layers board

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damian_s

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Hi guys,

I want to design a system using FPGA connected to an oscillator which has frequency 100MHz.

Is it possible to design a system using 100MHz oscillator frequency in two layers board?

Thanks.
 

If you are intending to use FPGA, so why do you need 100MHz???
You may use oscillator with less frequency to drive FPGA then you may use the internall PLL of the FPGA in order to produce any clock rate.

by low frequencies you may get best results considering EMI aspects.
 

Starting from a higher clean frequency can help a PLL for a smaller output jitter.
On two layer board the only way is grounded coplanar lines. But the frequency is still small for this tehnique.:D
You need a continous ground plane one one layer and a signal route surrounded by ground plane on the other layer.
Both ground planes must be connected with small vias (as many vias near the 100Mhz clock line on both sides of the signal line, as better).

On FR4 this works great up to 5Ghz.
52_1169922141.JPG
 

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    damian_s

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melc said:
Starting from a higher clean frequency can help a PLL for a smaller output jitter.
On two layer board the only way is grounded coplanar lines. But the frequency is still small for this tehnique.:D
You need a continous ground plane one one layer and a signal route surrounded by ground plane on the other layer.
Both ground planes must be connected with small vias (as many vias near the 100Mhz clock line on both sides of the signal line, as better).

On FR4 this works great up to 5Ghz.quote]

coooooooooooooooooooooool
what is this applications?
From here I may download it???
Click to expand...
 

Thank you for your reply.

If you are intending to use FPGA, so why do you need 100MHz???
You may use oscillator with less frequency to drive FPGA then you may use the internall PLL of the FPGA in order to produce any clock rate.
Click to expand...

Khaila, yes, I can use PLL to get my FPGA driven by high clock rate. From the specification I've got, there are different oscillator frequencies I can use and the highest is 100 MHz. I just want to know if there is anybody have an experience in implementing 100 MHz clock rate in two layers board.

Melc, thanks for the advice.
 

khaila said:
melc said:
Starting from a higher clean frequency can help a PLL for a smaller output jitter.
On two layer board the only way is grounded coplanar lines. But the frequency is still small for this tehnique.:D
You need a continous ground plane one one layer and a signal route surrounded by ground plane on the other layer.
Both ground planes must be connected with small vias (as many vias near the 100Mhz clock line on both sides of the signal line, as better).

On FR4 this works great up to 5Ghz.quote]

coooooooooooooooooooooool
what is this applications?
From here I may download it???
Click to expand...

Unfortunately it's a subrutine of microwave office, it won't work without the whole program which is copyleft, sorry.
But good news for you:D

https://www.skottanselektronik.com/ and click on impedance

melc codobelc
Click to expand...
 

You don't *really* need to use transmission line type stuff for 100Mhz if you keep everything small. I've done a 100MHz VCO & PLL on standard double-sided FR4 with no problem. Just don't make long lines.
 

You don't *really* need to use transmission line type stuff for 100Mhz if you keep everything small. I've done a 100MHz VCO & PLL on standard double-sided FR4 with no problem. Just don't make long lines.
Click to expand...

lladnar23,

Is 8 mil trace in standard FR4 board small enough? And could you be more specific about "don't make long lines", I mean how long is to long for a line?

Thanks.
 

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