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Floating point representation in HDL

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bh_letters

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$realtobits

Hi,

How are floating point numbers represented in HDL (verilog or vhdl)? If some one can explain with the addition of 2 floating numbers that would be great.

Thanks
 

realtobits

Here is how to use them in Verilog! Ofcourse its not synthesizable!
Hope this helps
Code:
/*
 $rtoi converts reals to integers w/truncation e.g. 123.45 -> 123
 $itor converts integers to reals e.g. 123 -> 123.0
 $realtobits converts reals to 64-bit vector 
 $bitstoreal converts bit pattern to real 
 Real numbers in these functions conform to IEEE Std 754. Conversion rounds to the nearest valid number. 
 */

module real_add(
   // Outputs
   sum, 
   // Inputs
   a, b
   );
   input [63:0] a;
   input [63:0] b;
   output [63:0] sum;
   real real_a, real_b;
   assign      sum = $realtobits(real_a + real_b);
   always @(a or b) begin
      real_a = $bitstoreal(a);
      real_b = $bitstoreal(b);
   end
endmodule // real_add


module test();
   reg [63:0]           a;
   reg [63:0]           b;

   wire [63:0]          sum;   

   real_add real_add(
                     // Outputs
                     .sum               (sum[63:0]),
                     // Inputs
                     .a                 (a[63:0]),
                     .b                 (b[63:0]));
initial begin
   $monitor ($time,,"a= %f b=%f sum = %f", $bitstoreal(a), $bitstoreal(b), $bitstoreal(sum));
   a = $realtobits(123.456);
   b = $realtobits(321.654);
   #10;
   a = $realtobits(111.111);
   b = $realtobits(222.333);
   #10;
   a = $realtobits(000.111);
   b = $realtobits(111.222);
   #10 $finish;
end
endmodule // test
 

bitstoreal

hi,
if u need a synthesisable code for impelment a floating point addition,
u have to implment the Floating point architecture using ur HDLs.
floating point addition is quite simple,
as it needs shifting and addition.
we need to align the mantissas wrt the exponent, and then just add both mantissas.

floating point architectures are available in all digital design books.
u can refer the ieee standards for the floating point numbers.

Rgds,
Renjith
 

$bitstoreal

Here is a link to an HDL design of a Floating Point Unit :
**broken link removed**


Description
This is a 32-bit floating point unit (FPU), which does arithmetic operations on floating point numbers. The FPU complies fully with the IEEE 754 Standard.


Features
FPU supports the following arithmetic operations:
Add
Subtract
Multiply
Divide
Square Root
For each operation the following rounding modes are supported:
Round to nearest even
Round to zero
Round up
Round down
Pipelined to achieve high operating frequency (100MHz with Cyclone EP1C6)
Tested with 2 million test cases
Hardware proven: FPU was implemented in a Cyclone I–EP1C6 FPGA chip and was then connected to the Java processor JOP(jopdesign.com) to do some floating-point calculations.

For more details please read the documentation. If that doesn't help, then post your question here: https://groups.yahoo.com/group/32bit_fpu/
 

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