Resistor mismatch in 10 bit DAC

resistor mismatch

Hello everyone,
I am designing a 10bit DAC in 90nm technology. The topology is Inverted Resistive ladder DAC and I am refering the IEEE paper "A Low Power Inverted Ladder D/A Converter" by Yevgeny Perelman and Ran Ginosar" for the design.I have the following general design questions:

1. I have got the values of the resistances from the paper but how to get the optimum sizes so that mismatch will be minimum

1. How to find out the effects of resistor mismatch in DAC. Which simulations do I perform in Cadence?

3. Can the mismatch be controlled in the layout only? Or are there and steps I need to so in the design of ladder DAC.
I am new to design so any help would be appreciated..
Thanks a lot in advance,
BR,
Vabzter

resistor missmatch

1. mismatch of two resistors, R is often given by:

dR/R = A / (W*L)
where W and L are dimentions of the resistor. A is a technology dependent paramter. So you must firts check process design kit.

2. A simple equation if to perfom one sweep (from 00..0 to 11..1b and determine the analog output. for each code then you can find INL.

bbbb said:

1. mismatch of two resistors, R is often given by:

dR/R = A / (W*L)
where W and L are dimentions of the resistor. A is a technology dependent paramter. So you must firts check process design kit.

2. A simple equation if to perfom one sweep (from 00..0 to 11..1b and determine the analog output. for each code then you can find INL.

Click to expand...

Hi bbbb,
Thanks for the reply but one more question..
Does the mismatch affect INL only or DNL too?
BR
Vabzter