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Xilinx FPGA Area Utilization

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pyrite

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xilinx fpga area report

I am confused on the area/map utilization report that I got from xilinx project navigator tools and i attached the report below.

(1) Which number is important in this report? What is my actual utilization now? I am planning to add in a few more blocks later. So I need to decide if i need to purchase a larger capacity of the virtex II or not.

(2) In the virtex II datasheet, the XC2V1500 has 1.5M system gates, and in my report, it said the equivalent gate count is 280K. Does that mean I only used 1/5 of the fpga resources? If not, what does these nunbers represent? How many of resources are used for interconnect?

Thanks in advance!

Design Information ------------------
Target Device : x2v1500
Target Package : fg676
Target Speed : -6
Mapper Version : virtex2
-- $Revision: 1.16.8.2 $ Mapped Date : Tue Jan 02 16:04:45 2007

Design Summary --------------
Number of errors: 0
Number of warnings: 20
Logic Utilization:
Number of Slice Flip Flops: 7,115 out of 15,360 46%
Number of 4 input LUTs: 14,346 out of 15,360 93%
Logic Distribution:
Number of occupied Slices: 7,678 out of 7,680 99%
Number of Slices containing only related logic: 6,424 out of 7,678 83%
Number of Slices containing unrelated logic: 1,254 out of 7,678 16%
*See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs: 14,630 out of 15,360 95%
Number used as logic: 14,346
Number used as a route-thru: 275
Number used as Shift registers: 9

Number of bonded IOBs: 104 out of 392 26%
IOB Flip Flops: 68
Number of Block RAMs: 2 out of 48 4%

Total equivalent gate count for design: 286,651
Additional JTAG gate count for IOBs: 4,992
Peak Memory Usage: 202 MB
 

number of slices fpga

Hi,

1). You should be looking at following two factors for actual fpga area utilization.
- Total no. of ocupied slices. (which is 99% in your case)
- Total no. of 4-input LUTs. (which is again 95%)

As i understand, Each slice has two LUTs and two flip-flops. By looking at the area report we can say your design is more of combinational logic than sequential logic. because FFs utilization is 47% where as LUTs utilization is more than 90%.

If you are planning to add some more logic which is more of sequential than combinational, i see some scope but if it is more of combinational i dont see any scope. The advice would be to put some extra logic in the design now itself and see how the device/tool behave in terms of area utilization.

The safest side would be to select a higher density device.

2). I think Gate count should not be considered for estimating area utilization. Our designs can not use each and every gate available on FPGA.

I hope these inputs help you.

Regards.
 

xilinx occupied slices

Thanks for your reply.
But in my understanding (correct me if I am wrong), the p&r will spread the logic around the whole fpga so maybe most of the occupied slices are not fully used. So will the Total no. of occupied slices be meaningful?

Is there a way that I can tell the tools to pack all the logic together and use the minimum number of slices?
 

area utilization xilinx

Hi,

what Aastik said is correct....and yes PnR tools does spread the logic a bit for timing but in your case the spreading does not seem to be more as LUT utilization is 95%....u could still add a liitle more logic if it does not affect your performance...then pnr will be able to do better packing....also i see only two block rams are being used...are u using any distributed rams ...again no fifo's for dsp slices...check if u can push some logic into dedicated resources of the fpga....

cheers
 

Anyone knows how to map the excess number of LUTs to unused BRAM or Distributed RAM ?
 

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