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VHDL coding styles to check the event of clock rising edge

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adamsogood

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Hi,

There are two VHDL coding styles to check the event of clock rising edge:

1. if (clk='1' and clk'event)
2. if (risingedge(clk))

Please suggest me which one is better? and why? Thanks a lot.
 

rising edge vhdl

#1 is more common and I believe has been in the VHDL spec longer. #2 is valid VHDL but looks more like Verilog. I would go with #1.
 

vhdl risingedge

both are Ok, #2 is defined in the ieee library, #1 is default vhdl
 

rising edge syntax vhdl

Yes..........there is no problem of using both the constructs.............

good luck
 

vhdl + rising edge

1: In this the statement below will execute when there is event on the clk and the clock =1 means the clock previous value may be O,Z,X among these values

2:but in this it will only from 0 to 1 transition not from Z,X

So, according to the need u can use,

If any changes , inform ...............
Thanks
ok
 

vhdl risingedge

Both coding styles are correct ...............you can use either one
 

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