Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Active low is faster way to reset than active high.It is in accordance with the rise and fall time issue. Active low reset is mostly used to avoid the noise and signal interference issues.
When we power up the system we want that our system should be resetted first instead of going through unwanted states. Active Low reset can be easily obtained by using an RC circuit. A sereis RC circuit is connected across Vcc and Gnd and the reset signal is tapped from the middle. When the power is applied, Initially the capacitor charge is zero and the reset pin is at gnd potential. The capacitor starts charging to Vcc, and thus the reset pin is at high potential. You can observe that the reset is always applied automatically at the power up for small period. the time is decided by the RC delay. With Active high reset, same auto reset can not be obtained.
Cheers
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
