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INL OF DAC POST LAYOUT

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amic

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the inl/ dnl plots of my dac show no change at 25 deg C and at cold temp. I understand this is becoz at schematic level there is no vth mismatch and so inl is very good ( simulated value - 0.0025LSB).

I guess i will have to do monte carlo to see the actual inl worst value. right ?
Also, I don't know how much layout will add to the mismatch ( in terms of magnitude of inl ) ? Anybody has got any idea?
 

Hi
I know that there is a mismatch mdel for it but I don't know it.
Can you explain more about your DAC and DNL/INL measurment method?
regards
 

hr_rezaee said:
Hi
I know that there is a mismatch mdel for it but I don't know it.
Can you explain more about your DAC and DNL/INL measurment method?
regards
Click to expand...

A simple test bench with ideal ramp given to ideal adc ( veriloga model ) creating 1024 codes given to DAC under test. Output of DAC is a stair case which is then tabulated to plot inl/dnl in matlab.
 

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