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Primetime: disabling timing of high fanout pins

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maverick_mind

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A pin of a gate is driving say 100 inputs of other gates. (eg net going from output of a nand gate to select pin of 100 muxes).

Proper buffering takes place during PnR. In pre layout STA, this pin will have a high transition and consequently high delay. This leads to timing violations.

Can anyone suggest me how to avoid high rise time associated with the pin. False path is one of the options but it may mask genuine violations.


thanks
 

set the output pins "ideal network"
 

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