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fpga doen't work correct

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torius

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Hallo again :)

My project is like this: i've got a moter encoder on a fpga, i'm counting the pulses and send the data throug i2c.

the problem is like this: every time i move the moter encoder, my fpga sometimes counts only for a sec and then doesn't response anymore. sometimes it counts wrong. it also can count only one way, so if i move left it crashes also.
but the simulation lets me see that it works correctly. i'm using altere cyclone 2. and just program with the byteblaster2. i'made a stade diagram in xilinx and convert it to verilog in altera.

so in short: everything is working theoraticly, but in real sometimes only for short, of sometime not at all

dus anyone knows what the problem could be?

regards,
Torius
 

Simulation is not the final phase in design, in many times simulation can give you wrong expectations as it simulates the both behavioral and RTL cdoes.

FPGA needs RTL designs only and not a behavioral one, so if you wrote a behavioral code then it will works for the simulation and will not work at FPGA.

Please check the synthesis report and read all warnings, if you found serious warnings like that of inferring a latch you have to redesign your modules again to meet RTL rules.

Good Luck.
 

Hallo,

I don't get any warnings, so i also don't know what's wrong. :(
and that you have 2 the same state diagrams for counting up and down, and that Only down works and up does it times it seems to "crash"

regards,
Torius
 

even if u don't have any warnings, your code simulates right but doesn't synthesize well
you have to try writing RTL code and follow its rules to avoid having extra latches or flipflops for instance
and as yasser said, simulation isns't the final phase, and good simulation doesn't indicate good synthesis

regards,
Salma
 

There are many things you can do to make your encoder interface versatile and "bullet proof." Here are a couple of the more important rules that apply:
  • Make a fully synchronous design. The entire design should use a single reference clock that is at least twice the highest encoder clock frequency. Do NOT attempt to clock any part of your sequential logic directly from the encoder clock signals.
  • Synchronize the encoder clocks. Be sure to synchronize the encoder's clock signals before they get into your sequential logic. You can do this by passing them through input flops which are clocked by the reference clock.
 

Thirst of all, thnx for the reactions, but it still doens't work :(:(,

does anyone else maybe have a suggestion?

Regards,
torius
 

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