joc_06
Member level 2
fixgatedclk
Hi,
Im sure this is a popular topic but Ive been having trouble with it recently.
Our asic clock gater has a latch in its design.
Now we are using Synplify pro to synthesize our design and in this appnote it says how to handle the gating: **broken link removed**
Basically on page 4 of that pdf it says only combinatorial gating can be used. IE we cannot use our latch version of our clock gater. But without our latch our design is not the same??
How can i model my clock gater for fpga? What must it contain?
Thanks for your help on this.
Hi,
Im sure this is a popular topic but Ive been having trouble with it recently.
Our asic clock gater has a latch in its design.
Code:
// OR
assign gentp = genp | scanen;
// Or instatntiation
// Latch:
always @(lclkp or gentp)
if (~lclkp) genlp <= gentp;
// Latch instatntiation
// AND
assign gclkp = genlp & lclkp;
// And instatntiationNow we are using Synplify pro to synthesize our design and in this appnote it says how to handle the gating: **broken link removed**
Basically on page 4 of that pdf it says only combinatorial gating can be used. IE we cannot use our latch version of our clock gater. But without our latch our design is not the same??
How can i model my clock gater for fpga? What must it contain?
Thanks for your help on this.
