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How to create variable input level front-end circuit for LA?

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JohnG300c

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Hello everyone.

I'm designing a MAXII-based device that will record timestamped data from a number of serial links. The idea is to upload this data via a FX2LP and display it in a PC application. I would like to be able to have a large, via software programmable input trigger range in the signal so it directly can be used for TTL and RS232 for example. The signal rate should be in the 4 Mbps rate to be able to capture very fast serial communication.

The question is: Are there any standard parts that would do this or will i have to create my own front-end using OP-amps? Will the OP-amps be fast enough for this application?

I do have a LogicPort (PcTestInstruments.com) Logic analyzer and it allows the input trigger level to be adjusted between -6V to 6V in 50mV increments. I took it apart but could not really figure out how it works. The Logicport uses an Altera Cyclone FPGA which has standard LVTTL input levels.


Thanks,
/John.
 

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