pianomania
Member level 5
We design a low power d flip-flop which will consume current when clock is switching , otherwise the current is very small when the clock is a stable state.
However, when the IC is startup , the clock source may rise to a meaningful voltage, say half of voltage supply(5V). Then the input stage of clock, like inverter which is constructed with pmos and nmos pair will turn on at this condition.
Then a meaningful current will flow from the power supply to the Pmos drain side to Nmos.
How to prevent this phenomenon ? To clamp the clock source output or modify the structure of inverter ? And what kind of inverter structure could be used ?
However, when the IC is startup , the clock source may rise to a meaningful voltage, say half of voltage supply(5V). Then the input stage of clock, like inverter which is constructed with pmos and nmos pair will turn on at this condition.
Then a meaningful current will flow from the power supply to the Pmos drain side to Nmos.
How to prevent this phenomenon ? To clamp the clock source output or modify the structure of inverter ? And what kind of inverter structure could be used ?
