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post-layout simulation

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hover

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Now I would like to run a post-layout simulation with sdf file back-annotated. The problem is that how I add the cell simulation verilog files of synthesis library into my final gate level netlist or verilog-xl simulator. There are more than 300 cell files, it's a very hard work to use include command to include all of them into my netlist. So what kind of measures can be taken to implement it.
 

Why dont you prepare a list file which will have all the verilog files as given in below example.

list file

"../../lib/add.v"
"../../lib/mult.v"
"./design.v"
"./test.v"

and then compile the design using below command

verilog -f file.list

note: creating list file

ls ../../lib/*.v > file.list

Hope this helps.
 

hello hover ..

i am not sure if this is correct answer, but may be u can trp this .. during synthesis for net list generation i guess ur not using the option of flatten .. if u can use this in ur script of DC the final generated netlist a single verilog life ,, u can use model sim with sdf file back annotation for post layout simulation .

please let me know if i am wrong , r u looking for it in other way..

suresh
 

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