Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Why signal should be stable in setup and hold window??

Status
Not open for further replies.
Do you mean why we need setup time and hold time in digital circuit? I have the same problem.
 

Do you mean why we need stable signal in digital circuit?
 

for this answer u need to analyze the circuit given for the positive edge triggered d-Flip flop circuit given in maris mano
 

according to what i understood from study of STA, if signal is not stable during setup or hold time then FF will not be able to identify correct input that can result in metastability or if not metastability then you might get output but not the expected ones.
 

If the signal is not stable before the setup time and continues to be stable till the hold time, the value captured by a flip-flop may not be correct.
 

Self study is the better way to understand this problem!
Just draw a flipflop with gates and assume some delays for each gate and try solving this by changing inputs at different time intervals. Then you can easily understand why u require a stable signal in between setup n hold time !!
 

Ok.....let me say in this way......................

This is my clock active edge ________|""""""""""
This is setup and hold times ....|tsu.....|..th..|......
This is my data signal ___________|'''''''''''''''''''''''
But due to paracities,
the data will be like this____________/""""""""""""
So at the active edge,the voltage sampled is not what we expected(0 r 5)....it may be around 2.5 v.......than........Flip Flop is a feedback circuit.........it takes much time for amplifying the 2.5 to 5v r 0v..........

I think I am able to convey my message.....some of then can understand it.......Please any one explain my concept clearly...so that others can understand it in a better way....
 

u can understand the D-flip-flop as two transfer gates.
IF signal did not stable in setup window,
THEN the signal is not captured correctly while the transfer gate closed!
IF signal did not stable in hold window,
THEN The recent data can substitute for the old data while the transfer gates are both open!
 

Just analyse yourself a D F/F with the input & the feedback given from Q and Qbar. Answer to your question is there in it.
 

otherwise you cannot capture the data.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top