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"Process varition"

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viren_s

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hi let us take a res ledder you have 16 res of different values and all are diveded into some combination of the unit res then does it require in layout to interleave them .
whats will be the effect if we are not interleaving them and puting them in a simple way( each res is a group of some unit res).
I know there will be the value changes due to the process gradient .but how critical it will be in 130 n.
over the block of res which is in the box of 50 u *100u.
thanks
 

In TSMC 130nm process, the device can match well in a long distance. you can ask your foundry for this issue
 

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