Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

loop bandwidth v.s reference frequency

Status
Not open for further replies.
Y

yijaylin

Newbie level 2
Joined
Aug 15, 2006
Messages
2
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,294
reference frequency loop bandwidth

hi:
when designing PLL, usually we say that the loop bandwidth need to be designed as 1/10 of reference frequency. I can't find the theorem about this. Could anyone expain it compendiously for me ? Or just tell me where to get the reference data. Thanks a lot!:D
 

first , when most of the new PLL use PFD or phase detector based on logic circuits like flip flops and so these components are discrete time not continues
and for main stream design we use the S domain for the design and model the PLL near lock state
so we always make the refernce frequency 10 times larger than the loop band width to make the continues time assumption is valid

khuoly
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top