How much current should pass through the rail and cascode in a folded cascode?

How do i decide how much current i should pass through the rail and cascode devices and how much through the nmos i/p diff pair(to tail current source) in afodled cascode config?

for eg: I want 100u passing through the tail source so i decide say 80:flows through to the folding node on the rail and cascode side(pmos side) and 30u to flow through the nmos side...is this fine?..min power dissipation spec is 0.75mW and 2.7v supply.I need a ugf of 5Mhz with a 5pf load..

rgds

southpaw

Re: folded cascode query

I think you meant that your MAXIMUM power dissipation spec is 0.75mW. For a 5MHz GBW with a 5pF load you need a gm of at least 25uS, this is assuming that your input transistors are not so big so as to make the input pole closer. So you need to decide a limit on the size of the input transistors based on the driving impedance of the source and then figure out what current you need to pass through them to get the desired gm.
To decide the current in the cascode string, keep in mind that you may want the current in each upper current source to be a little larger than 2 times the current in each input NMOS, so that during a full swing there will still be some current left in the cascode branch so that the fold transistor does not go into cut off and make your fold node to be a high impedance node. The other consideration to choosing the current in the cascode string is how much gain you want from your amplifier and where you want to place your output pole, i.e. what do you want the 3dB frequency to be.

Re: folded cascode query

Thanks a lot aryajur..
and yes it is max power dissipation...but i didnt understand on what basis I should decide the f3db right away...say i have 200uA flowing thru the tail current source under the diff amp...the diff amps share 100uA each..what i intend to set is 140uA flowing though the pmos transistors above the folding node..and the bottom nmos transistor section (current source)...will have the remaining 40uA...is this fine?..what i want to know if how i can figure the f3db from this......thanks in advance...

southpaw

Re: folded cascode query

Tell me if I understood correctly.. You are planning to have 100uA in each of the nmos input differential pair, so 200uA flows through the tail current source. And if you have 140uA each in the top sources so that leaves 40uA in each of the cascode strings.
The problem with this may be that if you have a large swing at the input and one of the nmos in the differential pair takes 140uA then there will be no current flowing in the cascode string so the transistor (pmos) whose source is connected to the fold will go into cutoff and it will make the fold node high impedance so you will loose your amplifying action.
The 3dB bandwidth would basically be determined by your Rout of the amplifier (w3dB=1/(Rout*C), which will decrease by increasing the current and increase by decreasing the current.

Re: folded cascode query

Yes that is correct...so what did you mean by slightly more than twice the current in each nmos input....

Re: folded cascode query

So, what I was suggesting was that suppose you have 100uA in each nmos in the input differential pair, so make the current in the cascode string a little more than 100uA.
Lets say you have 120uA in the cascode strings, this makes 220uA to flow in the upper current source transistors. That means even if the input differential pair has a swing so that 1 nmos takes all of the tail current (200uA)there will still be 20uA of current slowing in the cascode string.

folded cascode query

Hey Aryajur,

How did you arrive at a gm of 25uS? Maybe I am missing something very simple. Would appreciate if you could explain.
Thanks

Re: folded cascode query

I was using the expression that a gain bandwidth product for a dominant pole system is gm/C so gm = GBW*C hence 25uS.

Re: folded cascode query

Thanks aryajur and suhas_shiv....
aryajur,I didnt get your point about choosing the i/p transistor sizes based on the driving impedance of the source....all i need to maintain is a min gm of 25uS right?

southpaw

Added after 4 minutes:

moreover...i need 60 degree phase margin...so i guess the gm is a crucial parameter here...

Re: folded cascode query

The input transistor size will become important if the source that is driving your amplifier has some significant impedance since then there will be a pole created at the inputs of the amplifier and if the input transistors are large they will offer significant capacitance at the input node and this pole may come to lower frequency and destroy your phase margin.

Re: folded cascode query

as of now...i still havent figured out an efficient way to size transistors....do i need to charactarize each nmos and pmos separately(i.e keep a fixed gate and drain voltage and calculate w/l for the current i need) and then later put them all together into a circuit...or is there a better way of doing this?

southpaw

Re: folded cascode query

It depends on the transistor you are trying to size. If its the input pair, and you have already decided the current then size them to get the gm and the Vgs so that Vgs is not so big so that the lower level of your input common mode swing pushes the tail current source into triode region.
For the upper current sources, you need to make their W/Ls small to have better noise performance and to improve matching. The tradeoff you have to consider is their Vdsats since that will eat into your allowed output swing.
For the cascode transistors they need to match their Vgs so their W/L should be large, at the same time their ro should be large so as to make the fold node look like a low impedance towards them and most of the small signal current goes through them. The trande off is the noise performace.
The active current mirror is again like a current source so W/L small for improved matching and the trade off is the Vdsat for the output swing. You need to have large ro so that you have good gain.
This idea will let you start with initial W/L ratios relative to each other and then you can work your way to optimize them.
Try to characterize and get graphs of the nmos and pmos separately so that you get some idea how things are depending on the sizing for the technology. It may be useful to derive hand analysis parameters from the graphs themselves so that you can use them and get some initial sizes to start with and then simulate and optimize.

Re: folded cascode query

aryajur said:

For the cascode transistors they need to match their Vgs so their W/L should be large, at the same time their ro should be large so as to make the fold node look like a low impedance towards them and most of the small signal current goes through them. The trande off is the noise performace.

Click to expand...

why ro is large that make the fold node look like a low impedance towards them and most of the small signal current goes through them?what is mean of low impedance for fold node?

aryajur said:

The active current mirror is again like a current source so W/L small for improved matching and the trade off is the Vdsat for the output swing. You need to have large ro so that you have good gain.

Click to expand...

why small W/L for good matching?

thanks!

Re: folded cascode query

i think this is a basic question regarding Vds and VDsat.....suppose I have a 2.7 V supply...and i need a 2v p-p swing at the output....at the output i have a rail pmos,cascode pmos,rail nmos and cascode nmos.....i knw tht vds shud be greater than vdsat for all transistors to be in saturation...so is it the vds tht i shud be careful of while designing the ckt..in the sense i can only drop a total vds of 0.7 V over all the transistors(i.e 175mV each)..IS this correct?..and at the same time ensure that vdsat voltages are lesser thn the vds voltages.....

please comment..


thanks

southpaw.

Re: folded cascode query

Larger the ro the lesser impedance you see looking into the source node of a MOS device when there is a large resistance connected to the drain of the MOS. So a larger ro is desirable for the transistors with their source node connected to the folding node.
To minimize mismatch(due to process variations there is a mismatch between the threshold voltages of the 2 mirroring transistors) the vdsat of the mirror should be increased to whatever maximum can be tolerated. Once current is decided W/L should be reduced to increase the vdsat to the allowed margin. To know why Vdsat increasing minimizes current mismatch, just differentiate the current sq law equation assuming derivative of Vth is not 0. YOu can see the derivation in Gray and Meyer in the Biasing chapter, or in Art of Analog Layout book in one of its appendix.
So it may not be wise to just distribute the Vdsat limits on all the the transistors equally - give more quota for the mirroring transistors connected to the rail, lesser to the cascode transistors. Give more quota to the PMOS transistors since they have lesser mobility.

Re: folded cascode query

I still doesnt understand why do we need to increase the (W/L) of the cascode transistors in order to increase the ro of that transistor? Will increasing L alone keeping W constant wont suffice, since the ro is dependent on L alone....

Added after 5 minutes:

I do not understand how increasing the (W/L) of the cascode transistors helps me in matching their Vgs.

Re: folded cascode query

tshankar501 said:

I still doesnt understand why do we need to increase the (W/L) of the cascode transistors in order to increase the ro of that transistor? Will increasing L alone keeping W constant wont suffice, since the ro is dependent on L alone....

Added after 5 minutes:

I do not understand how increasing the (W/L) of the cascode transistors helps me in matching their Vgs.

Click to expand...

Yes ro is dependant on L, increasing L will increase ro, this is a trade off since to match Vgs you need to minimize the Vdsat of the transistors. As I said to know why try differentiating the Ids equation assuming Ids is constant. This is done for you in the book Art of Analog Layout Appendix.

Re: folded cascode query

Thanks for arjayur for making it crystal clear and for southpaw for having started this topic.....Thanks also to others for having their contributions...Now i think i understood the things...

Re: folded cascode query

the current load is 1.2-1.5 time of tail current

folded cascode query

Can i know how to determine the optimum voltage for simple folded cascode amplifier(1 NMOS and 1 PMOS)? The maximum and minimum range? thanks..