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How to abate frequency from 3 kHz to 2.7 kHz? (digital)

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Hello_world.

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hi guy.
i have some problem. I want to abate frequency from 3 KHz to 2.7 KHz.
Who can help or suggest me?
Thank you.
 

Re: clock dividers.

could u give more detail is it an analog signal or digital signal?
 

clock dividers.

I want to know in digital better. but must be not use DCM on FPGA.
Thank you.

Added after 8 minutes:

in my circuit use digital signal. I'll make HDD rpm control by use TDA5142T to drive moter HDD and use CPLD controll rpm. now when HDD spin around 5000 rpm will have frequency from TDA5142T around 3KHz but I want to use 2.7 kHz only.

Thank you.
 

Re: clock dividers.

I’m not sure, but
If you use PLL with /9 counter on the VCO loop you will get for 3kHz input 27Khz from the VCO output
Dividing the 27Khz with decade counter will give you output of 2.7Khz
 

clock dividers.

do you have link or ebook?
 

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