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If you want to know the transistor level eason of the setup/hold time, here is the idea.
On one hand, your data signal has to go through a transmission gate and charge the internal node with the cross-coupled inverters. The clock signal, on the other hand, just needs to "block off" the transmission gate.
Since data must go through more circuitry, it should be stable a little while before the active edge of the clock gets there.
Setup time and hold time constraint is the two main contraints for timing devices. Well setup time is also named the max-delay contraint,while hold time named min-delay contraint.So when computing setup time ,we should use the propagation delay(delay for the new data stable);and for hold time,use the contamination delay(delay for the old data start changing) .In additon , setup time constraint is related with clock period while hold time not.Adding the clock period will improve setup time contrait,but has no effect to hold time.
The time [before the active clock edge] after which any change in the input data could result in the FF latching the wrong value is characterized as the SETUP time of that DFF.
The time [after the active clock edge] for which the DFF output maintains its value before switching is characterized as the hold time for that DFF.
Added after 14 minutes:
The time [after the active clock edge] for which the DFF output maintains its value before switching is characterized as the hold time for that DFF.
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