alanmck
Newbie level 3
vhdl sine function simulation
Hi,
I created a RRC filter for an FPGA using ONEoverT from Tyder. The VHDL was created fine as well as all the test data and modelsim compile macro. However, when I simulate the design, I expect to see a sine wave at the output, but I don't.
I see output values however, but the it is not in an analog format.
The documents with the software show an example with the input data and the output data like real signals, but I am not seeing them with my design. Does anyone know how to display the signal correctly?
Thank you
Al
Hi,
I created a RRC filter for an FPGA using ONEoverT from Tyder. The VHDL was created fine as well as all the test data and modelsim compile macro. However, when I simulate the design, I expect to see a sine wave at the output, but I don't.
I see output values however, but the it is not in an analog format.
The documents with the software show an example with the input data and the output data like real signals, but I am not seeing them with my design. Does anyone know how to display the signal correctly?
Thank you
Al