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How to declare and define 2D array in VHDL?

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sivamit

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Hi how to declare and define 2D array in VHDL language.

type dataout is array (6 downto 0,11 downto 0) of std_logic;-is this correct?

But I dont know how to initialize this like a[0][1]=,a[0][2]= in C language.
Please help.
 

2d array vhdl

Ur 2D array declaration is correct..
Code: 
type dataout is array (6 downto 0,11 downto 0) of std_logic;

Initialization and use..
Code: 
library ieee;
use ieee.std_logic_1164.all;

entity test is
  
end test;

architecture behave of test is
type dataout is array (6 downto 0,11 downto 0) of std_logic;
signal a : dataout := ("000000000000", "000000111111", "101010101010",
                       "010101010100","111111111111","111111000000","111001100110");
signal b : std_logic;
begin  -- behave
  process
    
  begin  -- process
    for i in 0 to 6 loop
      for j in 0 to 11 loop
        b <= a(i,j);
        wait for 5 ns;
      end loop;  -- j
    end loop;  -- i
    wait;
  end process;

end behave;
 

2d array in vhdl

yah like nandgates said
u have to declare a signal from the type you made
and put the initialization values for it

but take care,you can only reference:
-the whole array --> array_2D
-a single element of the array --> array_2D(1,1) or array_2D (2,3) or whatever
-a slice of a 1-D array (u can't have a slice from a 2-D array) --> array_1D (7 downto 4) or array_1D (0 to 3)

Good luck,
Salma:)
 

vhdl multidimensional array

a 2d array can also be defined as follows.
type dataout is array (0 to 6) of std_logic_vector(0 to 7);
or
type dataout is array (0 to 6)of std_logic_vector(7 downto 0);

cheers,
 

array declaration in vhdl

but can it be declared like this

type Byte is array (7 downto 0) of std_logic;
type dataout is array (15 downto 0) of Byte;

isn't that also regarded also as a two dimensional array??? or a 1D array of a 1D array???
 

vhdl array declaration

hi Salma,
Well I think that a 2D array is nothing but a 1D array of 1D array and you have rightly given another option of declaring a 2D array.
I may stand corrected please...

cheers:))
 

vhdl array initialization

hi,

can i declare a 2D array as following ?

type dataout is array (6 downto 0,11 downto 0) of std_logic_vector(7 downto 0);

the element is std_logic_vector not std_logic

thanks
 

multidimensional array vhdl

wellll, actually i am confused a bit regarding this issue
that is what i thought, that they are both alike. but i read a while ago a comment somewhere that they are different and that people get confused between these two significations and they are not the same. so i just wanted someone who knows more to elaborate and we can all make benefit

maybe they are different cause you can then access a slice of the 1D array of 1D array,cause it is only seen as 1D of a "type", whatever that type can be (it may be a 1D array itself)........and if it was declared as 2D directly then you can access only individual elements and not whole slices

i got confused:(

Added after 2 hours 24 minutes:

addn said:
hi,

can i declare a 2D array as following ?

type dataout is array (6 downto 0,11 downto 0) of std_logic_vector(7 downto 0);

the element is std_logic_vector not std_logic

thanks
Click to expand...
i guess this is a 3D array not 2D
 

multidimensional array in vhdl

hi,

maybe VHDL support 1D,1D*1D,2D but not 2D*1D
 

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