sivamit
Full Member level 4
Hi how to declare and define 2D array in VHDL language.
type dataout is array (6 downto 0,11 downto 0) of std_logic;-is this correct?
But I dont know how to initialize this like a[0][1]=,a[0][2]= in C language.
Please help.
type dataout is array (6 downto 0,11 downto 0) of std_logic;-is this correct?
But I dont know how to initialize this like a[0][1]=,a[0][2]= in C language.
Please help.