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Hi
SDF standerd Delay format name itselft indicates it consisists of cell and net delays in different levels after the synthesis.
SDF is a standers whih is supported by all EDA tools.
Afetr performing the synthesis tools will generate SDF file w.r.t given libraies.
We can use this file for post simulation , Timing Analysis, or tool migration..etc ..
For more info u can look for SDF formats in sites.
--satya
we can get this file for a soc in various phases of ASIC flow
- Synthesis ( Wireload model , but not accurate)
- Cell Step ( Magma/PC/Jupitar , can be used to do GLS setup)
- After Placement ( For PC , used for GLS setup)
- After Detail Route ie P&R ( More realistic and accurate for Gate Level simulations)
every company will do the simulation of its rtl code for its function justifications. but in order to know that the designs is working in the real time or not they will simulate the netlist with the sdf.such that they can do the dynamic simulations on the design.it is only for the verifications.
sdf contains;
it cantains the delay cused by the each net and the cell in all the corners (i.e max,min,typ).
SDF stands for Standard Delay Format. This file contains delay information. For eg:
1. For combinational gates : The prop delay from change in input to change in output.
2. Sequential Cell: Clock-2-Out delays.
3. And also interconnect delays.
After Layout, parasitic-extraction is done. The output of these is usuall spef,dspf etc which cannot be used directly with netlist for simulation. Hence it is converted to SDF( SDF is generated based on the RC file).
Thus by using SDF in simulation you are making sure that the actual delay (layout) is being used for simulation.
This is back-annotation.
SDF stands for standard parasitic format.
there are generally delays associated with each digital gates bounded by some condition.these are called timing arcs.the annotator which is generally inbuilt to simulation tools looks the sdf file and functional model of the gate and checks whether the complete timing arcs are present in sdf file.It also looks for the consistency between gate level netlist , functional model and sdf file.
As it's said before,sdf is a kind of timing file . It can be generated from simulation model when we do pre-sim which not care for net delay. In post sim,we can extract RC delay from net parasited parameters. Then,we can give both net and gate delay for simulation, it is called back-annotation. I use NC simulator to do the simulation and debug patterns or testbench.
I'm not familiar with layout design, what flow and what tools do backend engineers use to provide SDF for post-sim?I wanna know some details.Thank you!
addtion: Another question is how can we get the delay infmation when condtions change, i mean operating voltage ,temperature and frequency vary in a range that called corners(mindelays,typdelays and maxdelays).
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