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Difference between simulation and test result of delayline?

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ericzhang

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In my design, an delayline is designed as an inverter chain with programmable
mos cap load.

The cap load is nmos: gate is connected to clock, bulk is connected to ground,
drain and source is switched between ground and vdd.

Now the chip test result shows the delay is smaller than what simulation shows.
The design is on UMC 0.13 technology.

Two questions:
1.Is the UMC model not precise in some condition?
2.Can i get more correct result by use varactor model?

Thanks!
 

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