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DESIGN OF LOW NOISE AMPLIFIER

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maybe , but i have designed some parts of LNB , i considered my frist element s the LNA , and the source of it is the horn which is 5 ohm source

khouly
 

[;)] maybe but if it is so, when you compute the overall link-budget considering the dish gain and equivalent antenna noise temperature and the LNB gain and noise figure you are neglecting the contribution of the horn...

...or the datasheet of the LNB must reports also the horn data...
 

I think the main factor, which determine the noise figure of the LNB is the LNA.
 

hi anybody tell how to design biasing networks for 1420Mhz LNa with 0.5 db NF....

and also i dont know how to do layout and fabrication using ADS ...so please if anybody knows abt this.....send me some information.

thank you
 

usually if u wnat a stable bias circuit , u need active bias one
so check on appnotes of agilent www.avagotech.com

and the bias line should be a thin microstrips "acts as RF chockes" to prevent RF from passing through it

and should be decoupled by using open stubs , or use a coil as RF choke and decoupling cap

khouly
 

hi khouly

i studied biasing networks for GaAs FETs in gonjalez book.in this book he has given some 6 biasing techiniques ,but the problem is how to choose the values of inductor and capacitor in that all the circuits .can you check the book once and tell me plzzzzz...my LNA specifications are fq:1420MHz
NF:0.5db.and also i want to know how to apply gate and drain voltages to the circuit using ADS.
 

the inductor should be RF high impedance so make it give u 10 or 20 times the impedance if u take a 50 ohm , then ur inductor ωL must be at least 500 , and also check the SFR of the inductor it should be at least be 3 times ur operation frequency
the capacitor must be RF short circuit so 1/ωc must be very low

note "u can replace the inductor by λ/4 microstrip line , with as high as possible Z0 , i mean as high as possible as narrow as u can get "

about the how to implement the bias network in ADS , first u should use nonlinear model not S parameter file , and study the DC behavior of ur FET and implement ur bias network , and run S parameter simulation with the nonlinear model , and the bias network

khouly
 

Please check "Design Guides" in ADS. It will help you to understand bias network.
 

hi khouly

thank you for your information... and now i have to fabricate my design work so can you tell me how to do layout in ADS,and how to select real values of R,L,C components .can you give some websites to search for componets.
waiting for your reply....
 

first of all u need to place the traces u will draw as a schematic components from the microstrip library in ads , and also u need to put the substrate definition u will use so ads can account the effect of these traces , then place the art work components these components have the layout "foot point " like smt 0603 or 0402

after finishing ur schematic , from the layout pull down menu , select generate layout
and then begin to select component by component in schematic and palce it in the layout
for components

www.murata.com
www.avx.com
www.yago.com
www.epcos.com

khouly
 

hi to all im designing 1420 LNA with NF 0.5 db.....i designed matching n/w and i stabilized my lna also but now i want to design a biasing network......for that anybody knows how to design bias n/w and how test the bias conditions etc....

i have designed bias n/w for my specifications also using one inductor 540nH and low impedance bypass capacitor but i dont know how to test my biasing n/w is correct or not.....please help me if anybody know....



thank you.......
 

u need to decide which topology for the bias network , like active , or passive
and also u need to check the bias lines , to isolate the RF signals from the DC network
by using RF choke inductors , and decoupling capacitors , or use the λ/4 narrow microstrip line , and wide stub to act as a capacitor

Khouly
 

hi khouly

i have selected passive n/w for my specifications and im sending my circuit also can u tell me is my circuit is correct or not if not wht are the mistakes..... and also tell me the remedies for my mistakes
 

from ur circuit i see that every bias point u but an inductor , and decoupling cap , and a small resistor , typically u connect the DC voltage at this point

am i correct , and did u check these network with nonlinear model

look on the circuit i have attached , the matching network inductor in the input will short the DC value of the input so the transistor will not work
i put a circle around it

khouly
 

hi khouly

iam showing all my circuits one by one

1)stability of transistor 1 with inductor 8nH and im choosing ATF 35143(2v,10ma).
and alos im attaching simulated output of this transistor also.


can you check this result is right or not.it will be helpful for me to check whether im going in rightway or not.

and one more thing is that im using utility for cstability and matching also...


thanks
 

hi khouly

2)now im attaching my 2 stage amplifier with matching circuits. but there is no output matching in my circuit because output impedance of transistor 2 is perfectly matched to 50 ohm load.

please can you see and tell me whether is it correct or not


and also im attaching the simulated result of this circuit. this time also i used utility from design guide. we used design guide---tools---smith chart for designing matching networks for this circuit.

thank u
 

hi khouly

3)now iam attaching my bias circuit. and i have no idea about biasing...so if my above all the circuits are perfect.

please can u design my biasing network for my specifications(fq:1420MHz,n.f<0.5db,bandwidth:20MHz,gain>20 db)for 2 stage amplifier one is

ATF 35143(2v,10ma)
ATF 35143(2v,15ma).

iam too much confuse about biasing.i cant get it anything.please help me again.


thanking you
 

in the parallel L's in the input matching try to add a series cap , which will be a short circuit in RF , to not effect the matching or use a coupling cap


about the bias , all u will add a RF choke coil in the RF with decoupling cap


khouly
 

hi khouly

i dont have an idea about dc biasing.just i have designed my biasing network with parallel inductor and decoupling capapcitor.i have taken help from others to build this bias network but now the problem is how to check my biasing network is correct or not....

how to calculate Vgs,Vg,Vd for biasing networks....

and i have selected ATF 35143 ,biasing point is 2v,10ma.

if possible can u design bias network for my specifications plz......i designed all the units but i strucked at this point so plzzzzz....design for me.

thanking you
waiting for reply
 

Dear halmstad

i have created a project with ads , and got the nonlinear model of the transistor , and foound that to get ur bias point u need a negative gate voltage about -.6 volt

if it is ok for u , u need to supplies

check on it and let me know , to proceed on designing bias network


khouly
 

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