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How is substrate connected to ground in all cells of Virtuoso layout?

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dsairajkiran

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Hello everyone,
My doubt is after drawing a layout in virtuoso.like std cells inverter,nand,oai etc
,in all these cells how is substrate connected to ground ,or to how take care that substrate is connected to ground.

thanks
 

virtuoso....inverter

hello Dsairaj kiran

There are many tutorial avaible online .. every uni using cadence tool for layouts has a tutorial starting with an interver .. please refer those .. i can one example tutiorail
**broken link removed**

please follow those steps .. u will get a better idea

suresh
 

virtuoso....inverter

You ensure that the substrate (or well) is connected to power/gnd by placing well taps. Generally you will put at least one well tap in every standard cell, or in a non standard cell design you will put a certain amount of well taps per area.
 

Re: virtuoso....inverter

eternal_nan said:
You ensure that the substrate (or well) is connected to power/gnd by placing well taps. Generally you will put at least one well tap in every standard cell, or in a non standard cell design you will put a certain amount of well taps per area.
Click to expand...

eternal_nan,my vss rail include following layers metal+ndiff+contact,contcats are many.is it sufficient to say that substrate is grounded.
 

Re: virtuoso....inverter

correct me if I am wrong but you dont need to ground the substrate.
You need to bias the wells (Nwells or Pwells) but not the substrate.

--cmos_dude
 

Re: virtuoso....inverter

cmos_dude said:
correct me if I am wrong but you dont need to ground the substrate.
You need to bias the wells (Nwells or Pwells) but not the substrate.

--cmos_dude
Click to expand...

Even we need to ground the taps right? Correct me if I understood incorrectly!
 

In the well taps, there two connections one for connecting nwell to vdd & other for connecting substrate to vss ..
 

curty said:
In the well taps, there two connections one for connecting nwell to vdd & other for connecting substrate to vss ..
Click to expand...

Exactly!>. But I have a doubt . Why we require p+ (in nMOS) to connect to vss? Why can't i directly use Metal to provide connection from vdd to substrate!!

- - - Updated - - -

Prashanthanilm said:
Exactly!>. But I have a doubt . Why we require p+ (in nMOS) to connect to vss? Why can't i directly use Metal to provide connection from vdd to substrate!!
Click to expand...

Correction:
Why can't i directly use Metal to provide connection from vss to substrate!
 

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