machael
Member level 2
verilog replication
hi all,
I found a strange problem in my design: I need to get the result of A*2^K, so I extend "A" by several 0s, like this:
{A,{K{1'b0}}}
K is a defined parameter in the module, it can be 0, 1, 2....
But, I found when I set K as 0, A will still be extended by 1 bit 0, that is, {0{1'b0}} is the same as {1{1'b0}}! Can anyone tell me why and how to solve it?
(I simulate my design by Modelsim 6.5g)
Thanks a lot!
hi all,
I found a strange problem in my design: I need to get the result of A*2^K, so I extend "A" by several 0s, like this:
{A,{K{1'b0}}}
K is a defined parameter in the module, it can be 0, 1, 2....
But, I found when I set K as 0, A will still be extended by 1 bit 0, that is, {0{1'b0}} is the same as {1{1'b0}}! Can anyone tell me why and how to solve it?
(I simulate my design by Modelsim 6.5g)
Thanks a lot!
