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VHDL question? And all bus bits?

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joc_06

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Just a quickie here:

How can i and all the bits of a bus to each other in VHDL?
eg

Code: 
bus <= match(2) and match(1) and match(0);

I just dont want to have to hard code the width of the bus as it may change through parameter's

What i have at the moment is:

Code: 
process (match)
variable result: std_logic;
begin
  result := '1';
  for i in match'range loop
    result := result and match(i);
  end loop;
  element_match <= result;
end process;

It works and simulates as id expect but in synthesis i am getting a crazy long combinatorial path which wont meet timing and i think it is due to this code. Note i have a few levels of this type of code in place.

Any idea's for a quick fix?
Thanks
John
 

Hi,
Which Synthesis tool are you using? Check if that tool supports built-in package as:

ieee.std_logic_misc

That package has AND_REDUCE as a function to do precisely what you are looking for. Interestingly their code is also similar to what you wrote. Usually synthesis tools have special understanding of these packages and hence tend to optimize it for your constraints. In your example, one can do lot of parallel and and keep logic levels to minimum (may be 2?)

HTH
Ajeetha, CVC
www.noveldv.com
 

    J

    joc_06

    Points: 2
    Helpful Answer Positive Rating
Hi, thanks for your reply.
I am using xst and ISE.

Basically i had an original design which worked fine and met timing BUT it didnt make use of any generate statements and wasnt very portable.

Now i required a similiar block elsewhere and i decided to re-code using generate's and process'es as above to make the block very customisable. This worked fine in simulation. However it is not meeting timing and has upto 2ns neg slack. I cannot figure out where this is coming from as the two designs are very similiar.

I will try what you say but i feel this is not the problem as my original code was good code and shouldnt infer any long paths.

I do have a small fear of using variable's in RTL code but still it should be good code.

Thanks
John

Added after 4 hours 59 minutes:

Just to update this:- My code was correct and it was inferring the correct logic.
My problem was in synthesis. My original design used different switches in MAP which caused better performance.
Once i updated MAP switches, i had positive slack and design passed timing.
Happy days!
Thanks
John
 

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