Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

diff between FIFO and RAM...

Status
Not open for further replies.
rakesh_aadhimoolam

rakesh_aadhimoolam

Full Member level 4
Joined
Mar 14, 2006
Messages
206
Helped
19
Reputation
38
Reaction score
2
Trophy points
1,298
Activity points
2,751
what is the diffeence between FIFO and RAM....

or how do we link both of these....
 

Hi,

FIFO is first in and first out.

RAM,should be used to store the data from FIFO.


Here, RAM, we have to depend on FPGA's RAM Block.


Please go through datasheet.(Xilinx)....
 

A Fifo is usual a dual-port RAM and includes two counters to point to the write and read addresses and some logic to indicate the FIFO status.
The dual port RAM in the case of synchronous FIFO and it can be quite harder in the case of async. FIFO
 

There is not address line in FIFO, full and empty signal instead.
 

I was talking about the internal structure :) of Fifo of course everybody knows there is no address lines in FIFO, I think of it as a circled RAM with two counters
 

hi

watever is said above is correct. I just want to add that "A FIFO doesn't provide u access to any random location i.e. its strictly on First In First Out basis, whereas a RAM has address lines so u can access any random location"

also FIFO is implemented using Dual Port Ram as said above
 
Something to add:
And in terms of FPGA implimentation both of the using either LUT or dual port RAM modules
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top