Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

TSMC process specific layer information

Status
Not open for further replies.
K

kumar123

Member level 3
Joined
Sep 5, 2006
Messages
57
Helped
9
Reputation
18
Reaction score
6
Trophy points
1,288
Activity points
1,639
rpo od tsmc

Hi Experts,
can anybody tell me what these layers meant? and specific requirement for TSMC library for resistor creation from layout or fab process perspective

layers: RPO , RH , RPDMY

i know that these RPO along with RH is used for salicidation (to reduce resistance), where as i see RPDMY is commonly present for both w/i and w/o salicidation.

Thanks in advance

Kumar
 

tsmc%resistor

RPDMY : Poly/ OD resistor dummy layer for LVS. Cutting edge of RPDMY over Poly/OD determines W/L of resistors. It's not mask layer.

RPO : Non silicided area definition. It's mask layer.

RH : ?? ( I can't find this layer )
 

od tsmc

Hi,
you can find out the information about this layer in LVS file. There it is mention that if you want to draw a poly resistor then it should contain POLY+RDUMY. This is dummy layer which define the area of poly which will be consider as resistor. I think,This will be transparent layer. If this layer is not available in your palette then you can get the information (no. of RDUMY layer) from DRC file and you can create a new layer in your pallete.
If I am wrong then please let me know.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top