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Verilog Reduction Operators & Logical Operators

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choonlle

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What is the difference between case1 and case2 ?

Case1:
if(&a[3:0])
b<=1'b1;


Case2:
if(a=4'b1111)
b<=1'b1;



Is that any difference in synthesis ??!!!
 

Hi,

It is the same. I've checked in synopsys dc.
 

    C

    choonlle

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but no of gates shall be different for both logic
 

They are same and there is not no diference between the two.
 

Since the behaviour modelling description is the same, it's possilble that the gates logic will be different.


But, which cases should be the best one?
 

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