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Syncrhonizing two data rates

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keerthivasan_bits

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I have to design a digital hardware block to synchronize a slower data rate from a network to a processor(working at higher data rate)...how should I go about the design ? should i use a PLL for this purpose ?
 

Hello!!

You can use a FIFO!
 

give a search for this topic,lot of material is available for implemeting FIFO
 

Usually, to synchronize between two clock domains, incase of signals, flopping the signals twice is done. For data FIFO is used.
 

you can use the slow clock as enable signal for high clock to sample data!!
 

you can use two phase handshake protocol

or use a asynchronous fifo (address should be gray coded)

best regards




keerthivasan_bits said:
I have to design a digital hardware block to synchronize a slower data rate from a network to a processor(working at higher data rate)...how should I go about the design ? should i use a PLL for this purpose ?
Click to expand...
 

you can exclusive two signals and send result as a feedback to first signal .
 

this is a classical topic in asic/fpga design. you can just google it.
 

the size of the fifo has relationship with the clock difference between them?
 

Put DFF BETWEEN YOUR Fast data rate i.e simply add an Buffer
Anmol
 

Using the Asynchronous FIFO is the best option by having some handshaking signals as every time the fast data rate should not wait for slower data rate while reading
 

1.handshaking

2.fifo
 

Hi
As the data needs to travel from slow clk to fast clk, It can be done using 2-3 stages of flip flops, these flip flops will be using the fast clk.

or alternatively afifos.....
 

Hi,
synchronization of what. data or control signal?

for control signal - dual rank synchronizers
for data - asynchronous fifo

-regards
-Manmohan
 

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