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difference b/w these two codes;i feel both yield same result

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elexhobby

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Hello,
I am a newbie to VHDL n reading Perry 9th chap.
I encountered the foll code where din and clk are IN ports n dout is OUT port -

SIGNAL q1,q2:BIT;
BEGIN
reg_proc:pROCESS
BEGIN
WAIT UNTIL clk'EVENT and clk = '1';
q1<=din;
q2=q1;
END PROCESS;
dout<=q1 WHEN en='1' ELSE
q2;

Here dout is declared outside the process. I can't see the difference that would take place if the dout statement was written inside the process. I know it has to do with delta delays, but still can't figure out what.

Plz help me. Thanks
 

Re: difference b/w these two codes;i feel both yield same re

elexhobby said:
I encountered the foll code where din and clk are IN ports n dout is OUT port -

Code: 
SIGNAL q1,q2:BIT;
BEGIN
reg_proc:PROCESS
BEGIN
 WAIT UNTIL clk'EVENT and clk = '1';
 q1<=din;
 q2=q1;
END PROCESS;
dout<=q1 WHEN en='1' ELSE
          q2;
Here dout is declared outside the process. I can't see the difference that would take place if the dout statement was written inside the process.
Click to expand...
When dout is placed in the process, it will not change until there is a clock event.

When dout remains outside the process, it can also change when en changes, independently from the clock signal.
 

Re: difference b/w these two codes;i feel both yield same re

Yes, the results shall be as mentioned by tkbits.
The dout will change as soon as enable is high independent of clock.
moreover the logic synthesis will yield a different result in both the cases.
 

Re: difference b/w these two codes;i feel both yield same re

Oh ya.. Thanks a lot!! Should have realized..
 

Re: difference b/w these two codes;i feel both yield same re

dout is asynchronous
doesn't depend on the clock signal
 

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