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folding Verilog("begin"-"end") code in G

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davyzhu

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Hi all,

I want to folding Verilog code in GVIM.

The Verilog code clause is "begin"-"end" pair. Is there any tutorial talk about how to use the folding in GVIM? And does GVIM support "begin"-"end" pair folding? Thanks!

BTW, my GVIM version is 6.2.

Best regards,
Davy
 

Re: folding Verilog("begin"-"end") code

Hi,
can you lcarify what is folding?

(Assuming that it is opening a begin and correctly closing it with a corresponding end, then
The gvim checks only paranthesis folding.
You need to develop a coding ethic of your own to check this out.
One way is intending.
begin
xxxx
xxxx
if (xxx)
begin
yyyy
yyyy
end
else
begin
zzz
zzz
end
xxxx
xxxx
end

Hope I cleared you.)
 

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