Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
A simple way is : using a delay line ( fabricated delay lines are available from different manufacturers) and use a fast logic circuit for AND the main pulse and delayed pulse.
if peak voltage is small not several ten volt
you can prepair odd number inverters and even number inverters
then take AND
if you use CMOS device for 130nm , the pulse width is around
the
single inverter propagation delay that is 50 pSEC without pad capacitor
nor LOAD capacitor
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
