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Fixing setup/hold violations on SoC Encounter

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steven852

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After running SoC Encounter with timing optimization, I still have a small amount of setup/hold violations to fix. They are around 20ps for hold and less than 6ps for setup. When I look at the timing reports, I think the hold time violations can be fixed by an ECO and the same as the setup violations. But I am not sure this is the right way to do that since the tool should be able to correct these violations. Any suggstions?

Thanks

Added after 56 minutes:

I forgot to say: setup and hold time analysis after pre CTS and post CTS are good. But setup/hold violations occur after post detail route.

Thanks.
 

The violations u have reported can be easily fixed by ECO,

Every time the tool may not give u the best timing,
and also looking into the timing violation values 20ps hold and 6ps setup, they can be fixed by using techniques like cell resizing, buffer insertion....
 

Hello au_sun,
Can you in detail how cell resizing and buffer insertion is done ? do you have to repeat layout synthesize after cell resizing and buffer insertion?

Dr.farnsworth
 

yeah, i fixed them with ECO. previously i made eco after add filler. for some unknown reasons, the eco didn't work.
 

in an eco, engineering change order, what parameters do one need to change?

hmm it would be nice if anyone can explain eco steps (flow)...


thanks,
Prasad
 

After I digged deeper into the ECO procdure, I realized there are much more to judge. I hope someone can share their experiences in doing ECO:

1. which fixing goes first, setup or hold? The basic question is that when fixing one of the them, the other won't be affected significantly. This large change is what I am experiencing: I can fix either of them easily but the other gets worse

2. which point to fix, datapath or clock tree? What I tried was in the datapath.

3. Which choice is better, inserting buffers or changing cells?

Thanks.
 

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