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how to write function in verilog

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dr.farnsworth

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illegal base specifier verilog

I want to change this function which is in vhdl into verilog

function char2vector (c : character) return std_logic_vector is
variable result : std_logic_vector(7 downto 0) ;
begin
case c is
--large letters
when 'A' => result := "01000001" ;
when 'B' => result := "01000010" ;
when 'C' => result := "01000011" ;
when 'D' => result := "01000100" ;
when 'E' => result := "01000101" ;
when 'F' => result := "01000110" ;
when 'G' => result := "01000111" ;
............

end case ;

return result ;
end char2vector ;
 

verilog base specifier in numeric constant

Why do you need this function in verilog???
You char in verilog you can directly assign to reg [7:0] and char2vec
happens automatically automatically .....
If you are not convinced... here is function in verilog
Code: 
function [7:0] char2vector;
   input [8*1:1] c;
   begin
      case (c)
         'A' : char2vector = 8'b01000001;
         'B' : char2vector = 8'b01000010;
         'C' : char2vector = 8'b01000011;
         'D' : char2vector = 8'b01000100;
         'E' : char2vector = 8'b01000101;
         'F' : char2vector = 8'b01000110;
         'G' : char2vector = 8'b01000111;
        ............
      end case ;
   end
endfunction
 

`define strings in verilog

i am writing a program to interface with lcd display

i get syntax error with this function

"'A": Illegal base specifier in numeric constant.
Expecting numeric digits.

Ist bec its expecting numeric digit rather than a character

but i need a function which takes a character

Added after 1 hours 31 minutes:

thanks nand_gates

i changed the 'A' to "A" in that case statements then it works :D

but why you defined the input like [8*1:1] ??
 

using `define string verilog

I defined the input like [8*1:1] this is the general practice to define string variables in Verilog.
For n long string variable I can write reg [8*n:1] str;
for more info see "Writing testbenches" book!
 

writing function in verilog

Thanks alot nand_gates i was searching how to define a string for longer time
 

verilog define str

dr.farnsworth said:
Thanks alot nand_gates i was searching how to define a string for longer time
Click to expand...
FYI - SystemVerilog has "string" data type as built in and is very powerful - not limited as plain Verilog way of "mimicing string using reg".

Check if your tool supports it. I know Questa & VCS supports it.

HTH
Ajeetha, CVC
www.noveldv.com
 

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