sakthi_tallika
Newbie level 6
Hi,
I am new to SystemC based verification/design. I am familiar with Vera/verilog/vhdl. I would like to learn SystemC in a systematic way. Is there any systemC methodology document like Vera rvm,Specman eRM? Please suggest some way to create a simple code and compile/simulate the code.
Regards,
sakthi.
I am new to SystemC based verification/design. I am familiar with Vera/verilog/vhdl. I would like to learn SystemC in a systematic way. Is there any systemC methodology document like Vera rvm,Specman eRM? Please suggest some way to create a simple code and compile/simulate the code.
Regards,
sakthi.