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    poly density rule

    hi

    I am doing DRC of my layout..

    It is showing the errors like

    PO.R.3 {@ Min poly area coverage < 14%
    DENSITY POLYi < 0.14 PRINT POLY_DENSITY.log
    }

    M1.R.1 { @ Min M1 area coverage < 30%
    DENSITY M1xd < 0.3 PRINT M1_DENSITY.log
    }


    M2.R.1 { @ Min M2 area coverage < 30%
    DENSITY M2xd < 0.3 PRINT M2_DENSITY.log
    }


    what are these errors..

    Also why we need to maintain so much minumum area of poly or metals..

    Can you pls tell me how it affects on fabricated chip..

    ..Regards
    ...savithru

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    layout density problem site:edaboard.com

    Hi,

    There are some DRC rules obligating that the denisty of certain layers in the layout does not get below or above a certain value.
    Usually these denisty rules exist for Metal and poly layers.
    They are not important at the block level design, but usually they are taken care of at the chip assembly step.

    Hope this helps.

    Regards,
    Shohdy



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    density rules sti

    Quote Originally Posted by savithru
    hi

    I am doing DRC of my layout..

    It is showing the errors like

    PO.R.3 {@ Min poly area coverage < 14%
    DENSITY POLYi < 0.14 PRINT POLY_DENSITY.log
    }

    M1.R.1 { @ Min M1 area coverage < 30%
    DENSITY M1xd < 0.3 PRINT M1_DENSITY.log
    }


    M2.R.1 { @ Min M2 area coverage < 30%
    DENSITY M2xd < 0.3 PRINT M2_DENSITY.log
    }


    what are these errors..

    Also why we need to maintain so much minumum area of poly or metals..

    Can you pls tell me how it affects on fabricated chip..

    ..Regards
    ...savithru
    One of the reason we need to maintain the minumum area is that we don't want the structure to be overetched.... Just imagine if you have small tiny poly structure far away from other poly structure..... this small poly will get etched more than the other poly..... Thus we have problem with the uniformity of the surface for the next process step..... This isolated poly also can be easily cracked under extreme temperature or voltage....


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    density rule in layout

    As already stated above, the uniformity requirements are in place for process reliability.


    However you don't need to meet the density rules manually, usually there are fill tools that come with your kit that will place dummy metal in areas where the density is too low.



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    what is density rule in layout

    Quote Originally Posted by atamez
    As already stated above, the uniformity requirements are in place for process reliability.


    However you don't need to meet the density rules manually, usually there are fill tools that come with your kit that will place dummy metal in areas where the density is too low.
    How about the maximum density rule..... Why do we have this rule?



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    density rule active dummy layer

    maximum density is exactly the opposite of the minimum density error. layers such as diffusion, poly and metals may exceed the allowable concentration per given area at chip level. when fabricating chips, the silicon is polished. it is preferable to have uniform concentration of all layers all through out the chip, so it would be polished uniformly. maximum density causes the chip to be polished unevenly, causing less dense areas to be polished out.



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    active dummy layer density rule

    DRC's flag up density errors in order to maintain the porosity in the certain layout.Porosity would be nothing but the ratio between routing area to cell total area.

    Keeping this in mind,porosity values have been decided for poly metal etc.When you exceed the limit ,then those kind of density errors flag up!!!!



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    maximum density error in layout

    The CMP ( Chemical Mechanical Planarization) process for the STI ( Shallow Trench Isolation) has been optimized as a trade off between junction leakage wich happens when the STI to ACTIVE step is too high, and transistor leakage (hump effect) which increases when the STI/ACTIVE step is too negative.
    However, the STI step uniformity is depending upon the ACTIVE density uniformity ; This is why insertion of dummy active areas (tiles) is mandatory if density constrainsts as described in the DRM are not reached.



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    Re: density rule in layout

    Quote Originally Posted by atamez View Post
    As already stated above, the uniformity requirements are in place for process reliability.


    However you don't need to meet the density rules manually, usually there are fill tools that come with your kit that will place dummy metal in areas where the density is too low.

    If I use tool they will fill dummy metal or poly for density maitain ... after that where it should will conected to ..(which net )??? (any how we can not leave the fills hanging it also leads some errors..knw..??)

    or if i do manulay where the dummy metal or poly fills should be connected..???



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    Re: density rule in layout

    Hi holla,

    After the dummy fill is done, we don't connect them to any potential.They are left floating in the layout. Leaving the dummy fill floating will not affect the circuit working because we take care of the drc rules which will specify spacing between the metal drawn layers and the metal dummy fill layers. If any net in the layout is parasitic critical, we usually don't put dummy fills over it to avoid any kind of capacitive effects if there are any.



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