Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Design a 1GHz Fully-Differential OP amp

Status
Not open for further replies.
shaq

shaq

Full Member level 5
Joined
Jul 23, 2005
Messages
311
Helped
14
Reputation
28
Reaction score
4
Trophy points
1,298
Activity points
3,397
0.35 op amp pdf

Dear all,

I want to design a 1GHz fully-differential OP amp with 70dB above of dc gain and 60 degree above of phase margin.

Can someone give me any suggestions?

Thanks for your replying.
 

This is almost impossible using the current processes...

Why would you need such fancy specs?
 

I assume 1GHz is the unity gain bandwidth of your opamp. Can you tell me how much the load capacitance is? A compensated opamp has a unity gain bandwidth of about (gm/CL)*0.5, where gm is the transconductance of the last stage.
 

gitarrelieber said:
I assume 1GHz is the unity gain bandwidth of your opamp. Can you tell me how much the load capacitance is? A compensated opamp has a unity gain bandwidth of about (gm/CL)*0.5, where gm is the transconductance of the last stage.
Click to expand...

CL is 1pF

I use TSMC 0.18 process and vdd is 1.8v.
 

hi,
maybe GeSi or GaAs is more rational for your spec.
 

Hi shaq,

Since you are using TSMC 0.18 process and vdd is 1.8v, you may calculate the transit frequency ft=3*u*(Vgs-Vth)/(4*pi*L^2) which should be around 1GHz if typical values are assumed.(u=650uA/V^2,Vov=0.2V) This means the target of designing 1GHz fully-differential OPamp is almost mission impossible for your chosen process.

As other posts mentioned, GaAs or SiGe may be reasonable choice for your target.
Hope it helps.

regards,
jordan76
 

fxxjssc said:
hi,
maybe GeSi or GaAs is more rational for your spec.
Click to expand...

I agrre to this....in BiCMOS process u will be getting more speed......particularly hetero precess (HBT).....like SiGe....etc...

u will be getting these from "austria microsystems" or "STMicroelectronics" etc. thru MOSIS (**broken link removed**) or CMP (http://cmp.imag.fr/index.php) third party vendor....but the fab cost is higher....


sankudey
 

Also you can run simulation about ft.
For tsmc0.18, the ft of pch3 nch3 pch nch are
20G 7.6G 7G and 1.6G with minmum L and vds=0.2V.
So you can choose high voltage device, but 1.8V is a little critical.
 

Is it correct the ft of pcn3 and nch3 (3.3 devices) are higher than pch and nch (1.8v devices) ? In my opinion, the design is possible.
 

ericliu said:
Is it correct the ft of pcn3 and nch3 (3.3 devices) are higher than pch and nch (1.8v devices) ? In my opinion, the design is possible.
Click to expand...

what about the threshold, it is higher for 3.3 V devices; so with 1.8 V supply design become too difficult and also don't know it will work for process coner.
 

What's your application? You can try bicmos or bipolar process
 

eezou said:
What's your application? You can try bicmos or bipolar process
Click to expand...

For high bandwidth of xDSL.
 

shaq,

do you need the 1GHz-Opamp for an active filter? Is the spec coming from an active RC filter embedding?
 

rfsystem said:
shaq,

do you need the 1GHz-Opamp for an active filter? Is the spec coming from an active RC filter embedding?
Click to expand...

No.

I want a "pure" fully-differential opamp, not included active RC filter.
 

Please refer to the paper "A 3-V 340-mW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR at nyquist input, jssc,vol. 36 no. 12 Dec. 2001". A two-stage amplifer has been presented with 100-dB of open loop gain and 2-GHZ GBW by using the 0.35-um CMOS process.
 

ericliu said:
Please refer to the paper "A 3-V 340-mW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR at nyquist input, jssc,vol. 36 no. 12 Dec. 2001". A two-stage amplifer has been presented with 100-dB of open loop gain and 2-GHZ GBW by using the 0.35-um CMOS process.
Click to expand...

Thanks, ericliu.

This paper is good but I think this architecture of opamp cannot work with 1.8v of Vdd.

The circuit of this paper is shown below.
 

shaq said:
Dear all,

I want to design a 1GHz fully-differential OP amp with 70dB above of dc gain and 60 degree above of phase margin.

Can someone give me any suggestions?

Thanks for your replying.
Click to expand...

Maybe this opamp architecture might help you meet the specs (this design simulated DC gain of 80 dB, GBW of 1.4 GHz and phase margin of 62 deg in TSMC 0.35 um CMOS technology) , though you may have have some difficulty with Vdd = 1.8 V :

**broken link removed**
**broken link removed**

Send me a PM if you want to discuss any details of the paper.

Bharath
 

Don't say it is impossible before thinking it over. Actually 1GHz GBW is normal in modern technologies. The difficult part is the output swing and high gain. A single-stage opamp might not be able to provide 70dB gain, furthermore, it's output swing in 1.8V is very small. However, a 2-stage opamp definitely meets your specs. The only thing I don't like in 2-stage opamps is the longer settling time.
 

I think it's quite possible with the technology u r using but it would be better if have access of BJT or HBT's in ur library..in the input stage u can use such BJT or HBT's which will provide u high ft at the same time u can use BJT or HBT's in the load part to get the high gain..but the architecture will be very difficult to bais properly.u can go for folded cascode topology(Ref. Razavi) by which u can have good gain,ph margin as well as UGB.. some CMFB circuit u have to put to stabilize the output C.M..u can use output stage depending on ur application.
 

tsb_nph said:
shaq said:
Dear all,

I want to design a 1GHz fully-differential OP amp with 70dB above of dc gain and 60 degree above of phase margin.

Can someone give me any suggestions?

Thanks for your replying.
Click to expand...

Maybe this opamp architecture might help you meet the specs (this design simulated DC gain of 80 dB, GBW of 1.4 GHz and phase margin of 62 deg in TSMC 0.35 um CMOS technology) , though you may have have some difficulty with Vdd = 1.8 V :

h**p://amsc.tamu.edu/SIS/Publications/pub/jounal/2006_8.pdf
h**p://amsc.tamu.edu/SIS/Publications/pub/jounal/2003_6.pdf

Send me a PM if you want to discuss any details of the paper.

Bharath
Click to expand...

I've used the topology described in these papers and it works very well. The amplifier I designed had specifications very similar to the ones the thread starter is wanting to meet. I think I had a larger supply voltage though.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top