Verification of the integration of an IP

Hi,

I want to run a test on my chip, and make sure that the IP I bought is integrated according to the vendor's specifications.
I added checks for each pin according to the behaviour it should have: i.e., check that the pin has a constant value of 1, or check if the pin gets a value of Z or X during the simulation, or check that a pin that shouldn't, doesn't toggle during the simulation.

Does anybody have another check that he/she thinks are worth adding?


Thanks in advance,

Sharas

can u pls try assertions.

sharas said:

Hi,

I want to run a test on my chip, and make sure that the IP I bought is integrated according to the vendor's specifications.
I added checks for each pin according to the behaviour it should have: i.e., check that the pin has a constant value of 1, or check if the pin gets a value of Z or X during the simulation, or check that a pin that shouldn't, doesn't toggle during the simulation.

Does anybody have another check that he/she thinks are worth adding?


Thanks in advance,

Sharas

Click to expand...

Few things to keep in mind in verifying 3rd party IPs.

1. It is good to have some redundancy in this process as you are never sure how much the IP has been verified to adhere to a standard spec.
2. Use a Verification IP from a vendore *different* from your Design IP vendor. This is key - don't ever use Design and Verification IP from same vendor.

3. For peripheral IPs (such as PCI, USB etc.), use Assertion IPs (AIP) as and when possible. Good examples are 0-in (Mentor) and Synopsys. Yes, there is redundancy bet'n AIP and VIP - but it is *good* one. You don't need to learn any new language, just plug it, get results/violation/coverage. Amazingly powerful and easy to use - fits into almost any flow - be it your TB in C/SystemC/Verilog/VHDL/SV/E/OpenVera etc.

Refer to SNUG India 2006 paper from RAMBUS for more on this topic.

Good Luck
Ajeetha, CVC
www.noveldv.com

Hi
I passed with this but we were the seller !!
The customer did the followinh
1- write assertions for the expected behaviour of the IP interface as speced by the standard or by design specificactions.
2- run VIP tools on the IP which is a tool that runs to test certain statndard protocol.
3- Build Bus functional models and use them to test the IP against it in a random test environment
4- Run Lint, CDC, Code Coverage on the design and face us with the results

Thanks