steven852
Advanced Member level 4
clock insertion delay
Doing a CTS in SoC Encounter, one observation is interesting. The clock insertion delay is not linear to the clock tree length. This is observed under the condition that all other logic on chip remains the same under the comparison except the clock tree shortened. I wonder why it is such.
Doing a CTS in SoC Encounter, one observation is interesting. The clock insertion delay is not linear to the clock tree length. This is observed under the condition that all other logic on chip remains the same under the comparison except the clock tree shortened. I wonder why it is such.