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duty cycles for CMOS output

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chang830

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we are deign a circuit with CMOS which is to convert the LVDS or other small signals to CMOS level. The output stage uses the inverter as buffer. I want to know, in normal, what about the duty cycles of this circuit? It can be limited into 45~55%?

Hope to share the experience from you.

Thanks in advance
 

First check the common mode of the LVDS small signal. If it is Vcc/2 (Vcc is the supply of the inverter, buffer) the PMOS and NMOS should be sized as per their mobility ratios. If the common mode voltage is either towards Vcc or GND size the PMOS and NMOS accordingly.
You need to make pull up and pull down circuits of equal strengths depending on the trip point (the common mode of the swing of LVDS small signal)

-Bharat
 

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