Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Fully differential output stage with low impedance

Status
Not open for further replies.
M

MayskiyJuk

Newbie level 5
Joined
Dec 16, 2005
Messages
10
Helped
1
Reputation
2
Reaction score
0
Trophy points
1,281
Location
Russia
Activity points
1,345
Common-mode voltage of the input differential signal is 1V. Vdd is 1.8V. What kind of output stage could a use to get several tens or hundreds KOhms? CM voltage of output diff signal approximatly 1V.
 

Do you need high or low output impedance out of the output stage? Your post heading says low impedance, value you want is in 10s or 100k range.

For input stage,either PMOS or NMOS differential is fine, athough NMOS is slightly better in terms of swing. To obtain high impedance at output you can use cascoded mirrors(e.g folded cascode) if you are happy with just 1 stage and its gain, or else use common source second stage.

1V common mode level is a good level to get good swings in either of the topologies.

If you are looking for low impedance at output, you can use a source follower buffer.
 
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top