How to use Environment Variable in VHDL testbench

vhdl testbench variable

Hi folks

I'm trying to read a testvector from my VHDL testbench to run a simulation using NC on linux. I want to point to the testvector file using an environment variable to make my testbench portable, but whenever I try to compile that testbench using NC, I get an error that the environment variable is not recognized. Given that this environment variable works file everywhere else .. so, how to solve this problem to be able to use environment variables inside VHDL testbenches on linux ?


Regards

environment variable vhdl

Maybe you can run NC-VHDL from inside a script and use a variable that way.

system variable now in vhdl

I effectively ran the NC from scripts .. but I do have a testbench written in VHDL , and I want to use the environment variable inside the VHDL as well ... to point to the location of the testvectro .. this was successful when using ModelSim under windows .. but with NC, it can't recognize the environment variables inside the VHDL .. it can only recognize the environment variables inside the scripts ..

any suggested solution ?

vhdl +environment variable

Anyone found anything about this problem ?? .. I'm waiting

testbench environment variables

i'm a verilog user, so, i use `include in my codes.

what is to be done is, from the place where the testbench is, the place of testcase is called, i.e.

assuming, testcases are under "/simulation/testcase" directory, and testbench is in "simulation/testbench" directory, the way to call testcase from testbench is,

`include "../testcase/test_name.v"

i'm not sure if a similar thing is possible in vhdl. will find out and let you know.

variable environnement vhdl

I tried to define my variable in the hdl.var but still when I invoke simvision it can't recognize the same variable .. though the hdl.var is read properly and when debugging the hdl.var it says that it recognizes the variable.

should I add the variable in a script specific to ncsim ? .. and how ?

how to use modelsim to testbench

omara007 said:

I effectively ran the NC from scripts .. but I do have a testbench written in VHDL , and I want to use the environment variable inside the VHDL as well ... to point to the location of the testvectro .. this was successful when using ModelSim under windows .. but with NC, it can't recognize the environment variables inside the VHDL .. it can only recognize the environment variables inside the scripts ..

any suggested solution ?

Click to expand...

This could become tool dependent. Usually I use GENERICs to keep testvector file location and change it using -g flag. WIth NC, you need to freeze it during elab time, Modelsim allows run time generics, perhaps new NC versions allow that.


Another, far easier option is to use:

Use inside VHDL a file named "test.dat" and use Unix links to change it on the fly.

For e.g.

ln -s /path/to/tests/test_1.dat ./test.dat

run one sim, then change it to:

ln -s /path/to/tests/test_2.dat ./test.dat

Infact this works even without quitting simulator - issue a reset then the new file is read!!

Not sure if this will fully solve your problem, it might!

Regards
Ajeetha, CVC
www.noveldv.com
New Book: A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
https://www.systemverilog.us/

using environment variables in vhdl

I need to do something like this is the VHDL testbench file :

#######################################

file_open(input_file,"$STIM/testvector.txt",read_mode);

#######################################

where input_file is declared in the reading process like this :
file input_file : text;

and $STIM is an environment variable = path to the directory under which I put my testvector.txt file.
Anyone can put the testvector file anywhere he wants, and just change the environment variable to his new path. All environement variables are put in a seperate file shipped with the project directory and is needed to be sourced in case someone will run the simulation.

P.S. What I want to do is indeed successful under ModelSim + Windows .. Now, my simulator is NC running under RHEL 4. I don't know how to do it under the new development environment.

Hope I made myself clear ..

Waiting for your contributions

vhdl test bench generics

Hi,
Your requirement/intention is clear, however given that you yourself have seen that the way to approach it is not compatible across tools/platforms, how about slight change in the way you achieve the same?

1. You have $STIM that user will set before running sim.
2. You use that inside VHDL as of today.

What I proposed is:

1. You simply use local PATH to the file, without any $STIM inside your VHDL code.

2. Ask user to set up the $STIM/testvector.txt link to local file before running sim. (That anyway he does in previous way as well, see step #1 above).

I'm not sure if you loose any flexibility if you do it the new way, I don't see one.

Ajeetha, CVC
www.noveldv.com
New Book: A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
https://www.systemverilog.us/