What are PADS? PAD to SETUP delays? PAD to PAD delays?

Hi,

I saw these delays in XILINX ISE Timing Contraints Editor... What do they mean? How can I calculate accurate values for these for my designs?

pad

A pad is the physical bonding pad on an integrated circuit. All signals on a chip must enter and leave by way of a pad. Pads are connected to package pins in order for signals to enter or leave an integrated circuit package.

You Use It In Timing Constrains :

PADS Is Pre-Defined Group :

Using predefined groups, you can refer to a group of flip-flops, input latches, pads, or RAMs by using the corresponding keywords.

PADS - All I/O pads (typically inferred from top level HDL ports)


Predefined Group Examples
UCF syntax:
TIMESPEC “TS01”=FROM FFS TO FFS 30;
TIMESPEC “TS02”=FROM LATCHES TO LATCHES 25;
TIMESPEC “TS03”=FROM PADS TO RAMS 70;
TIMESPEC “TS04”=FROM FFS TO PADS 55;
TIMESPEC “TS01” = FROM BRAMS_PORTA TO BRAMS_PORTB(gork*);

You can find the definitions of these in the Glossary.